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VT82C580VPX
REVISION HISTORY
Document Release Preliminary Date 1/2/97 Revision Original release based on VT82C595 Apollo VP2 data sheet revision 0.4 (VPX register set is more like Apollo VP2 than like VT82C580 Apollo VP) * Changed intro and features list to reflect Apollo VPX * Added pinouts, electrical, and mechanical specs from 580VP data sheet * Added tables of pins in alphabetical order for both chips * Changed pinouts to reflect VPX - Removed UMA (added CPURSTI and CPURSTO on MREQ0/1#) - Added 64Mb DRAM support (added MA12/13 opt on MBEN/RAS5) - Improved SDRAM support (added SWEC#/SCASC# on WE/Mgnt) * Changed registers to reflect VPX - Removed ECC registers (no pins for ECC in PQFP package) - Added Rx50[2], Rx65[2], Rx66[5], Rx68[3], Rx6B[2] - Swapped bytes of Rx54-55 & 56-57 to match silicon (same in VP2) Initials DH
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Preliminary Revision 0.1 January 9, 1997 -iRevision History
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VT82C580VPX
TABLE OF CONTENTS
REVISION HISTORY........................................................................................................................................................................I TABLE OF CONTENTS.................................................................................................................................................................. II LIST OF FIGURES..........................................................................................................................................................................III LIST OF TABLES ...........................................................................................................................................................................IV OVERVIEW ....................................................................................................................................................................................... 3 PINOUTS ............................................................................................................................................................................................ 5 VT82C585VPX PINOUTS.............................................................................................................................................................. 5 VT82C587VP PINOUTS............................................................................................................................................................... 11 REGISTERS ..................................................................................................................................................................................... 14 REGISTER OVERVIEW ................................................................................................................................................................. 14 CONFIGURATION SPACE I/O ....................................................................................................................................................... 15 REGISTER DESCRIPTIONS............................................................................................................................................................ 16 PCI Configuration Space Header........................................................................................................................................ 16 VT82C585VPX-Specific Configuration Registers ............................................................................................................. 17
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Cache Control ....................................................................................................................................................................................... 17 DRAM Control ..................................................................................................................................................................................... 19 DataShee PCI Bus Control.................................................................................................................................................................................... 23
.com ELECTRICAL SPECIFICATIONS............................................................................................................................................... 25
ABSOLUTE MAXIMUM RATINGS ................................................................................................................................................. 25 DC CHARACTERISTICS................................................................................................................................................................ 25 AC TIMING SPECIFICATIONS ...................................................................................................................................................... 26 PACKAGE MECHANICAL SPECIFICATIONS ........................................................................................................................ 49 PQFP-208 .................................................................................................................................................................................... 49 PQFP-100 .................................................................................................................................................................................... 50
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Preliminary Revision 0.1 January 9, 1997 -iiTable of Contents
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VT82C580VPX
LIST OF FIGURES
FIGURE 1. APOLLO VPX SYSTEM BLOCK DIAGRAM......................................................................................................... 3 FIGURE 2. VT82C585VPX PIN DIAGRAM (TOP VIEW) ......................................................................................................... 5 FIGURE 3. VT82C585VPX PIN LIST (ALPHABETICAL ORDER) ......................................................................................... 6 FIGURE 4. VT82C587VP PIN DIAGRAM (TOP VIEW) .......................................................................................................... 11 FIGURE 5. VT82C587VP PIN LIST (ALPHABETICAL ORDER) .......................................................................................... 12 FIGURE 6. DRAM READ PIPE LINE EDO 5-2-2-2, 3-2-2-2 .................................................................................................... 30 FIGURE 7. POST WRITE 3111,DRAM EDO 2222 .................................................................................................................... 31 FIGURE 8. SDRAM READ CYCLE (BANK INTERLEAVE, CAS LATENCY=3) ................................................................ 32 FIGURE 9. SDRAM WRITE CYCLE (BANK INTERLEAVE) ................................................................................................ 33 FIGURE 10. CPU READ HIT SYNCHRONOUS SRAM 3111 .................................................................................................. 34 FIGURE 11. CPU WRITE HIT SYNCHRONOUS SRAM 3111................................................................................................ 35 FIGURE 12. CPU READ MISS FILL SYNCHRONOUS SRAM .............................................................................................. 36 FIGURE 13. CPU READ MISS DIRTY L2 WRITE BACK FILL............................................................................................. 37 FIGURE 14. CPU READ PCI SLAVE.......................................................................................................................................... 38 FIGURE 15. CPU WRITE PCI SLAVE WRITE BUFFER ON FAST BACK TO BACK ...................................................... 39 FIGURE 16. PCI MASTER READ HIT DRAM.......................................................................................................................... 40 FIGURE 17. PCI MASTER READ L1 SNOOP TO DRAM....................................................................................................... 41 FIGURE 18. PCI MASTER READ HIT L2 ................................................................................................................................. 42 FIGURE 19. PCI MASTER READ L1 SNOOP TO L2............................................................................................................... 43 FIGURE 20. PCI MASTER WRITE DRAM ............................................................................................................................... 44 FIGURE 21. PCI MASTER WRITE HIT L1 SNOOP TO DRAM ............................................................................................ 45 FIGURE 22. PCI MASTER WRITE HIT L2 ............................................................................................................................... 46 t4U.com FIGURE 23. PCI MASTER WRITE HIT L2, L1 HITM ............................................................................................................ 47 DataShee FIGURE 24. PCI MASTER WRITE HIT L2 & DIRTY ............................................................................................................. 48 FIGURE 25. MECHANICAL SPECIFICATIONS -.com FLAT PACKAGE.................................................. 49 208-PIN PLASTIC FIGURE 26. MECHANICAL SPECIFICATIONS - 100-PIN PLASTIC FLAT PACKAGE.................................................. 50
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Preliminary Revision 0.1 January 9, 1997 -iiiList of Figures
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VT82C580VPX
LIST OF TABLES
TABLE 1. VT82C585VPX PIN DESCRIPTIONS ......................................................................................................................... 7 TABLE 2. VT82C585VP VS. VT82C585VPX PINOUT DIFFERENCES SUMMARY............................................................. 9 TABLE 4. VT82C587VP PIN DESCRIPTIONS .......................................................................................................................... 13 TABLE 5. VT82C585VPX REGISTERS ...................................................................................................................................... 14 TABLE 6. SYSTEM MEMORY MAP.................................................................................................... ...................................... 19 TABLE 7. AC TIMING MIN / MAX CONDITIONS.................................................................................................................. 26 TABLE 8. PAD LOAD DERATING CURVE (I/V CURVE) ...................................................................................................... 26 TABLE 9. AC CHARACTERISTICS - CPU CYCLE TIMING ................................................................................................ 27 TABLE 10. AC CHARACTERISTICS - L2 CACHE TIMING ................................................................................................. 28 TABLE 11. AC CHARACTERISTICS - DRAM INTERFACE TIMING................................................................................. 28 TABLE 12. AC CHARACTERISTICS - PCI CYCLE TIMING................................................................................................ 29 TABLE 13. AC CHARACTERISTICS - DATA TIMING .......................................................................................................... 29
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Preliminary Revision 0.1 January 9, 1997 -ivList of Tables
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VT82C580VPX
VIA VT82C580 APOLLO VPX
LOW-COST PENTIUM / PCI NORTH BRIDGE WITH 66/75MHZ CPU SUPPORT AND SDRAM / EDO / FPG INTERFACE FOR GREEN PC DESKTOP COMPUTERS
* Flexible CPU Interface - Supports 64-bit PentiumTM, AMD 5K86TM , AMD 6K86TM and Cyrix 6X86TM CPUs - CPU external bus speed up to 75 MHz (asynchronous) or 66MHz (synchronous) (internal 200Mhz and above) - Supports CPU internal write-back cache - System management interrupt, memory remap and STPCLK mechanism - Cyrix 6X86 linear burst support - CPU NA# / Address pipeline capability Low Cost - PQFP packaging for low-cost implementation of 64-bit Pentium-CPU, 64-bit system memory, and 32-bit PCI - VT82C580 Apollo VPX Chipset: VT82C585VPX system controller and VT82C587VP Data Buffers - VT82C586B includes UltraDMA-33 EIDE, USB, and Keyboard / Mouse Interfaces plus RTC / CMOS - Six TTLs for a complete main board implementation PCI/ISA Green PC Ready - Supports 3.3V or 5V interface to CPU, system memory, and / or PCI bus - Supports CPUs with internal voltages below 3.3V - PC-97 compatible using VT82C586B South Bridge with ACPI Power Management Advanced Cache Controller - Direct map write back or write through secondary cache - Pipelined burst synchronous SRAM (PBSRAM) cache support - Flexible cache size: 0K/256K/512K/1M/2MB - 32 byte line size to match the primary cache - Integrated 10-bit tag comparator - 3-1-1-1 read/write timing for PBSRAM access at 66/75 MHz - 3-1-1-1-1-1-1-1 back to back read timing for PBSRAM access at 66/75 MHz - Sustained 3 cycle write access for PBSRAM access or CPU to DRAM and PCI bus post write buffers at 66/75 MHz - Data streaming for simultaneous primary and secondary cache line fill - System and video BIOS cacheable and write-protect - Programmable cacheable region and cache timing
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Preliminary Revision 0.1 January 9, 1997 -1Features
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* Fast DRAM Controller - - - - - - - - - - - - - - - - - - - - - *
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VT82C580VPX
Fast Page Mode/EDO/Synchronous-DRAM support in a mixed combination Mixed 1M/2M/4M/8M/16MxN DRAMs 6 banks up to 512MB DRAMs Flexible row and column addresses 64-bit or 32-bit data width in arbitrary mixed combination 3.3v and 5v DRAM without external buffers Two-bank interleaving for 16Mbit SDRAM support Two-bank and four bank interleaving for 64Mbit SDRAM support (14 MA lines) Four cache lines (16 quadwords) of CPU/cache to DRAM write buffers Concurrent DRAM writeback Speculative DRAM access Read around write capability for non-stalled CPU read Burst read and write operation 4-2-2-2 on page, 7-2-2-2 start page and 9-2-2-2 off page timing for EDO DRAMs at 50/60 MHz 5-2-2-2 on page, 8-2-2-2 start page and 11-2-2-2 off page timing for EDO DRAMs at 66 MHz 6-1-1-1 on page, 8-1-1-1 start page and 10-1-1-1 off page for SDRAMs at 66 MHz 5-2-2-2-3-1-2-2 back-to-back access for EDO DRAM at 66 MHz 6-1-1-1-3-1-1-1 back-to-back access for SDRAM at 66 MHz BIOS shadow at 16KB increment Decoupled and burst DRAM refresh with staggered RAS timing Programmable refresh rate, CAS-before-RAS refresh and refresh on populated banks only
Intelligent PCI Bus Controller - - - - - - - - - - - - - - - - - -
32 bit 3.3/5v PCI interface DataShee Synchronous divide-by-two and asynchronous PCI bus interface PCI master snoop ahead and snoop filtering .com PCI master peer concurrency Synchronous bus to CPU clock with divide-by-two from the CPU clock Automatic detection of data streaming burst cycles from CPU to the PCI bus Five levels (double-words) of CPU to PCI posted write buffers Byte merging in the write buffers to reduce the number of PCI cycles and to create further PCI bursting possibilities Zero wait state PCI master and slave burst transfer rate PCI to system memory data streaming up to 132Mbyte/sec Forty-eight levels (double-words) of post write buffers from PCI masters to DRAM Sixteen levels (double-words) of prefetch buffers from DRAM for access by PCI masters Enhanced PCI command optimization (MRL, MRM, MWI, etc.) Complete steerable PCI interrupts Supports L1 write-back forward to PCI master read to minimize PCI read latency Supports L1 write-back merged with PCI master post-write to minimize DRAM utilization Provides transaction timer to fairly arbitrate between PCI masters PCI-2.1 compliant
* * * *
Built-in nand-tree pin scan test capability 0.6um mixed voltage, high speed / low power CMOS process VT82C585VPX: 208-pin PQFP Package VT82C587VP: 100-pin PQFP Package
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Preliminary Revision 0.1 January 9, 1997 -2Features
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VT82C580VPX
OVERVIEW
The VT82C580VPX Apollo-VPX is a high performance, cost-effective and energy efficient chip set for implementation of PCI / ISA desktop and notebook personal computer systems based on 64-bit P54C/Pentium/K5/K6/M1 super-scalar processors. The CPU / cache connection is supported using an "asynchronous" interface up to 75Mhz CPU external bus speed (with CPU internal speed up to 200Mhz and above), with CPUs such as the "P200+" processors from Cyrix / IBM Microelectronics. The "asynchronous" interface allows the processor external bus frequency to be increased above 66MHz while still allowing the PCI bus to run at the specified top frequency of 33MHz. The chipset also supports CPU external bus speeds up to 66MHz in "synchronous" mode, so may also be used in boards designed around the popular VT82C580VP (Apollo VP) chipset. The 66MHz external bus speed is used primarily for Intel and AMD processors. The CPU, DRAM and PCI bus are all independently powered so that each of the bus can be run at 3.3v or 5v, independently. The ISA bus always runs at 5v. The VT82C580VPX chip set consists of the VT82C585VPX system controller, the VT82C586B PCI to ISA bridge, and two instances of the VT82C587VP data buffers. The VT82C585VPX is the only different component in a VPX-based system from the chips used in an Apollo VP system: the same VT82C586B South Bridge chip may be used with all VIA North Bridge chips (Pentium and PentiumPro-based designs) and the VT82C587VP Data Buffer is the same chip as is used in Apollo VP designs.
The CPU bus is minimally loaded with only the CPU, secondary cache and the chip set. The VT82C587VP data buffers isolate the CPU bus from the DRAM and PCI bus so that CPU and cache operation may run reliably at the high frequencies demanded by today's processors. The VT82C585VPX contains multiple deep FIFOs to allow efficient concurrent operation and DRAM utilization. The VT82C586B PCI to ISA bridge includes integrated 206-style IPC (DMA, interrupt controller and timer), integrated keyboard controller with PS2 mouse support, integrated DS12885 style real time clock with extended 256 byte CMOS RAM, ACPI-compatible Power Management subsystem, integrated master mode enhanced IDE / UltraDMA-33 disk controller with full scatter and gather capability, and integrated USB (universal serial bus) interface with root hub and two function ports with built-in physical layer transceivers (refer to the separate VT82C586B Data Sheet for additional information). A complete t4U.com DataShee main board can be implemented with only six TTLs. Refer to Figure 1 for the system block diagram.
P54C/K5/K6/M1 CPU CA
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VT82C585VPX MA/RAS/CAS 208PQFP PCI VT82C586B 208PQFP
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VT82C587VP 100PQFP
ISA/IDE USB
Figure 1. Apollo VPX System Block Diagram
The secondary (L2) cache is based on Burst Synchronous (Pipelined or non-pipelined) SRAM cache modules from 128KB to 2MB. For burst synchronous SRAMs, 3-1-1-1 timing can be achieved for both read and write transactions at 66Mhz. Four cache lines (16 quadwords) of CPU / cache to DRAM write buffers with concurrent write-back capability are included in the VT82C587VP data buffer chips to speed up cache read and write miss cycles. The VT82C580VPX supports six banks of DRAMs up to 512KB. The DRAM controller supports Standard Page Mode DRAM, EDO-DRAM, and Synchronous DRAM in a flexible mixed/match manner. Synchronous DRAM allows zero wait state bursting between the DRAM and the VT82C587VP data buffers at 66/75Mhz. The six banks of DRAM are grouped into three pairs with
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Preliminary Revision 0.1 January 9, 1997 -3Overview
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VT82C580VPX
an arbitrary mixture of 256K/512K/1M/2M/4M/8M/16MxN DRAMs. Each bank may be populated with either 32bit or 64bit data width. The VT82C580VPX supports the shadowing of the system, video and other BIOS to speed up access. The video and system BIOS can also be write-protected and made cacheable. Access cycles to either E , D or C segment can be programmed to be an on-board EPROM cycle to allow the combination of system and video BIOS for an all-in-one system board implementation. The VT82C580VPX can also be programmed to recognize write cycles as EPROM cycles to support field upgradability of flash EPROM BIOS. The VT82C580VPX supports a 3.3/5v 32-bit PCI bus with 64-bit to 32-bit data conversion. Five levels (doublewords) of post write buffers are included to allow for concurrent CPU and PCI operation. Consecutive CPU addresses are converted into burst PCI cycles with byte merging capability for optimal CPU to PCI throughput. A 16-bit fast data link is established between the two VT82C587VP data units and the VT82C585VPX system controller so that the address, data and command information for CPU to PCI bus transactions is contained in the same chip. This arrangement, unique to the VT82C580VP and VT82C580VPX chipsets is crucial in achieving zero wait state buffer movement and implementing sophisticated and upgradable buffer management schemes such as the byte merging. For PCI master operation, forty-eight levels (doublewords) of post write buffers and sixteen levels (doublewords) of prefetch buffers are included for concurrent PCI bus and DRAM/cache accesses. The chipset also supports enhanced PCI bus commands such as Memory-Read-Line, Memory-Read-Multiple and Memory-Write-Invalid commands to minimize snoop overhead. In addition, the chipset supports advanced features such as snoop ahead, snoop filtering, L1 write-back forward to PCI master and L1 write-back merged with PCI post write buffers to minimize PCI master read latency and DRAM utilization. The VT82C586B PCI to ISA bridge supports four levels (doublewords) of line buffers, type F DMA transfers and delayed transactions to allow efficient PCI bus utilization and is PCI-2.1 compliant.
The integrated master mode IDE controller of the VT82C586B supports a dual-channel / four-device enhanced IDE bus with enhancements for UltraDMA-33 operation and has sixteen levels of double-word prefetch and write buffers. The data bus, control signals, write buffers and prefetch buffers are separated from those of the PCI bus so that performance and electrical loading are t4U.com optimized. The command and recovery time of each IDE device can be individually programmed in units of PCI bus clocks to DataShee achieve optimal speed of the device up to 33MB/s. Other features of the IDE controller include interlaced dual channel commands, full scatter and gather capability, bus master programming interface for ATA controllers, SFF-8038 compliance and .com complete software driver support. The VT82C586B South Bridge also includes an integrated RTC with extended 256-byte CMOS, integrated keyboard controller, integrated USB (Universal Serial Bus) controller, and a sophisticated power management unit that is compliant with both APM 1.1 and ACPI 0.9 to allow design of PC systems that are fully PC-97 compliant. The VT82C580VPX is ideal for high performance, high quality, high energy efficient and high integration desktop and notebook PCI/ISA computer systems.
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VT82C580VPX
PINOUTS
VT82C585VPX Pinouts
Figure 2. VT82C585VPX Pin Diagram (Top View)
(DQM2#) (DQM6#) (DQM0#) (DQM4#) (DQM1#) (DQM5#) (DQM3#) (DQM7#) O 104 (MA13) O 103 O 102 (CS1#) O 1 0 1 (CS0#) O 1 0 0 (CS3#) O 9 9 (CS2#) O 9 8 97 96 (SWEC#) O 95 (CE1#) O 9 4 (SCASB#) O 93 (SCASA#) O 92 (BWE#) O 91 (GWE#) O 90 O 89 (DB32) IO 8 8 IO 8 7 IO 8 6 IO 8 5 84 83 IO 8 2 IO 8 1 IO 8 0 IO 7 9 IO 7 8 IO 7 7 (SWEB#) O 76 (SWEA#) O 75 (SRASB#) O 74 (SRASA#) O 73 O 72 (CADS#) O 71 (CADV#) O 70 I 69 I 68 I 67 I 66 O 65 O 64 O 63 O 62 61 60 I 59 I 58 O 57 O 56 I 55 I 54 I 53 (MA12) REQ2# GNT1# REQ1# GNT0# REQ0# SCASC# CPURSTO GND VDD CPURSTI AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 GND CBE3# AD23 AD22 AD21 AD20 AD19 AD18 GND VDD-PCI AD17 AD16 CBE2# FRAME# IRDY# TRDY# DEVSEL# STOP# LOCK# PAR SERR# CBE1# AD15 AD14 AD13 GND VDD-PCI AD12 AD11 AD10 AD9 AD8 CBE0# AD7 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208
O 156 I 155 O 154 I 153 O 152 IO 1 5 1 IO 1 5 0 IO 1 4 9 IO 1 4 8 147 IO 1 4 6 IO 1 4 5 IO 1 4 4 IO 1 4 3 142 O 141 O 140 O 139 O 138 O 137 O 136 O 135 IO 1 3 4 IO 1 3 3 IO 1 3 2 IO 1 3 1 IO 1 3 0 IO 1 2 9 IO 1 2 8 IO 1 2 7 O 126 O 125 O 124 O 123 O 122 O 121 O 120 119 O 118 O 117 O 116 O 115 114 O 113 O 112 O 111 O 110 O 109 O 108 O 107 O 106 O 105
GNT2# REQ3# GNT3# PREQ# PGNT# PLINK15 PLINK14 PLINK13 PLINK12 VDD PLINK11 PLINK10 PLINK9 PLINK8 GND CMD4 CMD3 CMD2 CMD1 CMD0 HSTB# MSTB# PLINK7 PLINK6 PLINK5 PLINK4 PLINK3 PLINK2 PLINK1 PLINK0 CMD5 MA11 MA10 MA9 MA8 MA7 MA6 GND MA5 MA4 MA3 MA2 VDD-DRAM MA1 MA0 CAS2# CAS6# CAS0# CAS4# CAS1# CAS5# CAS3#
I O I O I O O I IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO I IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO
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Note: Pin names in parentheses (...) indicate alternate function
CAS7# RAS5# RAS4# RAS1# RAS0# RAS3# RAS2# VDD-DRAM GND WE# CALE CWE3# CWE2# CWE1# CWE0# TWE# TA9 TA8 TA3 TA4 VDD-CPU GND TA5 TA6 TA7 TA2 TA1 TA0 CWE7# CWE6# CWE5# CWE4# COE# A3SEL A4SEL W/R# HITM# D/C# ADS# EADS# BOFF# NA# BRDY# VDD-CPU GND HCLK SMIACT# AHOLD KEN#/INV CACHE# M/IO# HLOCK#
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Preliminary Revision 0.1 January 9, 1997 -5VT82C585VPX Pinouts
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GND AD6 AD5 AD4 AD3 AD2 AD1 AD0 PCLK VDD-CPU CA23 CA21 CA24 CA27 GND CA22 CA26 CA25 CA28 CA31 CA3 CA30 CA29 CA4 CA7 CA6 GND CA5 CA8 CA11 CA10 CA16 CA17 CA18 CA19 CA20 CA9 GND CA12 CA14 CA13 CA15 VDD-CPU BE7# BE6# BE5# BE4# BE3# BE2# BE1# BE0# RESET#
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
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Figure 3. VT82C585VPX Pin List (Alphabetical Order)
Pin No 71 70 8 7 6 5 4 3 2 208 206 205 204 203 202 199 198 197 186 185 182 181 180 179 178 177 174 173 172 171 170 169 168 167 66 57 51 50 49 48 47 46 45 44 64 62 91 21 24 28 26 25 29 37 31 30 39 41 40 Pin Name A3SEL / CADS# A4SEL / CADV# AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 ADS# AHOLD BE0# BE1# BE2# BE3# BE4# BE5# BE6# BE7# BOFF# BRDY# BWE# / CWE1# CA3 CA4 CA5 CA6 CA7 CA8 CA9 CA10 CA11 CA12 CA13 CA14 Pin No 42 32 33 34 35 36 12 16 11 13 18 17 14 19 23 22 20 55 71 70 94 109 107 111 105 108 106 110 104 207 196 187 176 94 137 138 139 140 141 126 72 166 163 100 101 98 99 90 91 92 93 73 74 75 76 67 88 191 109 Pin Name Pin No CA15 107 CA16 111 CA17 105 CA18 108 CA19 106 CA20 110 CA21 104 CA22 65 CA23 188 CA24 1 CA25 15 CA26 27 CA27 38 CA28 60 CA29 83 CA30 96 CA31 119 CACHE# 142 CADS# / A3SEL 164 CADV# / A4SEL 175 CALE / CE1# 183 CAS0# / DQM0# 200 CAS1# / DQM1# 160 CAS2# / DQM2# 158 CAS3# / DQM3# 156 CAS4# / DQM4# 154 CAS5# / DQM5# 90 CAS6# / DQM6# 59 CAS7# / .com DQM7# 68 CBE0# 53 CBE1# 136 CBE2# 189 CBE3# 56 CE1# / CALE 193 CMD0 54 CMD1 112 CMD2 113 CMD3 115 CMD4 116 CMD5 / MA12 117 COE# 118 CPURSTI 120 CPURSTO 121 CS0# / RAS0# 122 CS1# / RAS1# 123 CS2# / RAS2# 124 CS3# / RAS3# 125 CWE0# / GWE# 126 CWE1# / BWE# 103 CWE2# / SCASA# 135 CWE3# / SCASB# 63 CWE4# / SRASA# 194 CWE5# / SRASB# 9 CWE6# / SWEA# 152 CWE7# / SWEB# 127 D/C# 128 DB32 / TA9 129 DEVSEL# 130 DQM0# / CAS0# 131 Pin Name DQM1# / CAS1# DQM2# / CAS2# DQM3# / CAS3# DQM4# / CAS4# DQM5# / CAS5# DQM6# / CAS6# DQM7# / CAS7# EADS# FRAME# GND GND GND GND GND GND GND GND GND GND GND GND GND GNT0# GNT1# GNT2# GNT3# GWE# / CWE0# HCLK HITM# HLOCK# HSTB# IRDY# KEN#/INV LOCK# M/IO# MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 MA10 MA11 MA12 / CMD5 MA13 / RAS5# MSTB# NA# PAR PCLK PGNT# PLINK0 PLINK1 PLINK2 PLINK3 PLINK4 Pin No 132 133 134 143 144 145 146 148 149 150 151 153 100 101 98 99 102 103 161 159 157 155 52 92 93 162 195 58 73 74 192 75 76 95 77 78 79 86 85 82 81 80 87 88 190 89 147 165 10 43 61 84 97 114 184 201 69 95
VT82C580VPX
t4U.com
Pin Name PLINK5 PLINK6 PLINK7 PLINK8 PLINK9 PLINK10 PLINK11 PLINK12 PLINK13 PLINK14 PLINK15 PREQ# RAS0# / CS0# RAS1# / CS1# RAS2# / CS2# RAS3# / CS3# RAS4# RAS5# / MA13 REQ0# REQ1# REQ2# REQ3# RESET# SCASA# / CWE2# SCASB# / CWE3# SCASC# SERR# SMIACT# SRASA# / CWE4# SRASB# / CWE5# STOP# SWEA# / CWE6# SWEB# / CWE7# SWEC# / WE# TA0 TA1 TA2 TA3 TA4 TA5 TA6 TA7 TA8 TA9 / DB32 TRDY# TWE# VDD VDD VDD-CPU VDD-CPU VDD-CPU VDD-CPU VDD-DRAM VDD-DRAM VDD-PCI VDD-PCI W/R# WE# / SWEC#
DataShee
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Table 1. VT82C585VPX Pin Descriptions
Signal Name Pin No. Power I/O Signal Description
VT82C580VPX
Clock Control
HCLK 59 CPU I Host Clock. This pin receives a buffered host clock which is used by all VT82C585VPX logic in the Host CPU clock domain. This pin should connect to the same clock net that is used to clock the CPU. PCI Clock. Used by all logic in the PCI clock domain. Typically host clock divided by two for 66MHz CPU operation but is not required to be synchronous with HCLK. Maximum 33MHz to meet PCI specifications.
PCLK
9
CPU
I
Reset Control
RESET# CPURSTI CPURSTI 52 166 162 PCI PCI CPU I I O Reset. Resets the chip and sets all register bits to their default values. CPU Reset In. Used to synchronize the CPURST signal from the south bridge chip to the CPU (required for 75MHz operation, optional for 66). CPU Reset Out. Synchronized CPURST signal to the CPU.
CPU Interface
ADS# M/IO# W/R# D/C# t4U.com BE#[7:0] CA[31:3] 66 54 69 67 44-51 20, 22-23, 19, 14, 17-18, 13, 11, 16, 12, 3632, 42, 40-41, 39, 30-31, 37, 29, 25-26, 28, 24, 21 62 65 56 68 CPU CPU CPU CPU CPU CPU I I I I I B Address Strobe. The CPU asserts ADS# in T1 of the CPU bus cycle. Memory / IO Write / Read Data / Control Byte Enables. Indicate byte lanes accessed in the current CPU cycle. Address Bus. CA[31:3] connect to the address bus of the CPU. During .com are inputs. These signals are driven by the CPU cycles CA[31:3] VT82C585VPX during cache snooping operations.
DataShee
BRDY# EADS# KEN#/INV HITM#
CPU CPU CPU CPU
O O O I
HLOCK# CACHE#
53 55
CPU CPU
I I
AHOLD NA# BOFF# SMIACT#
57 63 64 58
CPU CPU CPU CPU
O O O I
Bus Ready. The VT82C585VPX asserts BDRY# to indicate to the CPU that data is available on reads or has been received on writes. External Address Strobe. Asserted by the VT82C585VPX to inquire the L1 cache when serving PCI master accesses to main memory. Cache Enable / Invalidate. KEN#/INV functions as both the KEN# signal during CPU read cycles and INV during L1 cache snoop cycles. Hit Modified. Asserted by the CPU to indicate that the address presented with the last assertion of EADS# is modified in the L1 cache and needs to be written back. Host Lock. All CPU cycles sampled with the assertion of HLOCK# and ADS# until the negation of HLOCK# must be atomic. Cacheable. Asserted by the CPU during a read cycle to indicate the CPU can perform a burst line fill. Asserted by the CPU during a write cycle to indicate that the CPU will perform a burst write-back cycle. Address Hold. AHOLD is asserted while PCI masters are accessing main memory. AHOLD is held for the duration of PCI burst transfers. Next Address Back Off. Asserted by the VT82C585VPX when required to terminate a CPU cycle that was in progress. System Management Interrupt Active. This is asserted by the CPU when it is in system management mode as a result of an SMI.
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Cache Control
COE# CWE#[7:0] / SWE#A-B, SRAS#A-B, SCAS#A-B, BWE#, GWE# TWE# A3SEL / CADS# 72 76-73, 93-90 CPU CPU O O
VT82C580VPX
89 71
CPU CPU
O O
A4SEL / CADV#
70
CPU
O
TA[9] / DB32 TA[8:0]
88, 87, 80, 81, 82, 85, 86, 7977 94
CPU
B
t4U.com CALE / CE1#
CPU
O
Cache SRAM Output Enable Multifunction Pins: Global write option off (Rx50[2] = 0): Cache SRAM Write Enables for each byte. Global write option on (Rx50[2] = 1): Synchronous DRAM Command indicators and BWE#/GWE# for global write SRAM control. Tag Write Enable. When asserted , new state and tag addresses are written into the external tag. Multifunction Pin: Async SRAM: Cache Address 3. A3SEL is used to sequence through the Quad-words in a cache line during a burst operation. Sync SRAM: Cache Address Strobe. Assertion causes the burst SRAM to load the BSRAM address register from BSRAM address pin. Multifunction Pin: Async SRAM: Cache Address 4. A4SEL is used to sequence through the Quad-words in a cache line during a burst operation. Sync SRAM: Cache Advance. Assertion causes the burst SRAM to advance to the next Quad-word in the cache line. Tag Address. These are inputs during CPU accesses, outputs during L2 cache line fills, and L2 line invalidates during inquire cycles. TA9 is a multi-function pin and will act as DB32 to the VT82C587VP chips when 32-bit DRAM mode is enabled. Multifunction Pin: DataShee Async SRAM: Cache Address Latch. CALE is used to control the cache address latches. .com Sync SRAM: Chip Enable 1. CE1# is used as chip-select 1 for BSRAM.
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DRAM Control
MA[11:0] MA12 / CMD5 125-120, 118115, 113-112 126 DRAM DRAM O O Memory Address. DRAM address lines 0-11.
VT82C580VPX
RAS5# / MA13
103
DRAM
O
RAS4# RAS[3:0]# / CS[3:0]# CAS[7:0]# / DQM[7:0]# SRASA#, SRASB#
102 99-98, 101-100 104, 110, 106, 108, 105, 111, 107, 109 73, 74
DRAM DRAM DRAM
O
O
Dual Function Pin: Command 5. This function is provided for backwards compatibility: In VT82C585VP-based designs (i.e., non-VPX), this pin (previously called "MBEN#) was connected to the VT82C587VP "CMD5" pin for UMA control. For compatibility with those systems, this pin may be programmed to remain high at all times. In new or modified designs, the VT82C587VP CMD5 input may be tied high so that this pin may be used to drive Memory Address 12 for support of larger memory sizes. FPG/EDO/BEDO DRAM: Row Address Strobe for bank 5 or Memory Address 13. Synchronous DRAM: Memory Address 13 FPG/EDO/BEDO DRAM: Row Address Strobe for bank 4 Synchronous DRAM: Unused FPG/EDO/BEDO DRAM: Row Address Strobe for each bank. Synchronous DRAM: Chip Select for each bank. FPG/EDO/BEDO DRAM: Column Address Strobe for each byte lane. Synchronous DRAM: Data Mask for each byte lane.
DRAM
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SCASA#, SCASB#, SCASC# SWEA#, SWEB#, SWEC# / WE# 92, 93 DRAM
75, 76, 95
DRAM
FPG/EDO/BEDO DRAM: Inactive. Synchronous DRAM: Row Address Command Indicators (three identical copies for better drive). DataShee O FPG/EDO/BEDO DRAM: Inactive. .com Synchronous DRAM: Column Address Command Indicators (three identical copies for better drive). O FPG/EDO/BEDO DRAM: Write Enable (pin 95). Pins 75-76 inactive. Synchronous DRAM: Write Enable Command Indicators (three identical copies for better drive).
O
VT82C587VP Interface
PLINK[15:0] 151-148, 146143, 134-127 DRAM B
PCI Link. This is the data path between CPU / main memory and the PCI bus. PCI main memory reads and CPU-to-PCI writes are driven onto these pins by the VT82C587VP. CPU reads from PCI and PCI writes to main memory are received on this bus by the VT82C587VP. Each VT82C587VP is connected to one byte
MSTB# HSTB# CMD[4:0]
135 136 141-137
DRAM DRAM DRAM
O O O
of this bus. Memory Strobe. Assertion causes data to be posted in the DRAM Write Buffer. Host Strobe. Assertion causes data to be posted in the CPU Read Buffer. Command. The VT82C585VPX uses these signals to control the buffers in the VT82C587VP chips. See also pin 126 above for CMD5 function.
Table 2. VT82C585VP vs. VT82C585VPX Pinout Differences Summary
Pin # 95 103 126 162 163 166 VT82C585VP WE# RAS5# MBEN# MGNT# MREQ0# MREQ1# -9VT82C585VPX WE# / SWEC# RAS5# / MA13 CMD5 / MA12 SCASC# CPURSTO CPURSTI VT82C585VPX Pinouts
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PCI Bus Interface
FRAME# AD[31:0] 188 167-174, 177182, 185, 186, 197-199, 202206, 208, 2-8 176, 187, 196, 207 189 190 192 191 PCI PCI B B
VT82C580VPX
Frame. Assertion indicates the address phase of a PCI transfer. Negation indicates that one more data transfer is desired by the cycle initiator. Address / Data Bus. The standard PCI address and data lines. The address is driven with FRAME# assertion and data is driven or received in following cycles.
C/BE#[3:0]
PCI
B
IRDY# TRDY# STOP# DEVSEL#
PCI PCI PCI PCI
B B B B
PAR SERR# LOCK#
194 195 193 153 152 155, 157, 159, 161 154, 156, 158, 160
PCI PCI PCI PCI PCI PCI PCI
B B B I O I O
t4U.com
PREQ# PGNT# REQ#[3:0] GNT#[3:0]
Command / Byte Enable. Commands are driven with FRAME# assertion. Byte enables corresponding to supplied or requested data are driven on following clocks. Initiator Ready. Asserted when the initiator is ready for data transfer. Target Ready. Asserted when the target is ready for data transfer. Stop. Asserted by the target to request the master to stop the current transaction. Device Select. This signal is driven by the VT82C585VPX when a PCI initiator is attempting to access main memory. It is an input when the VT82C585VPX is acting as a PCI initiator. Parity. A single parity bit is provided over AD[31:0] and C/BE[3:0]. System Error. The VT82C585VPX will pulse this signal when it detects a system error condition. Lock. Used to establish, maintain, and release resource lock on the PCI bus PCI Request. This signal comes from the south bridge chip (VT82C586, 586A, or 586B). PREQ# is the south bridge chip's request for the PCI bus. DataShee PCI Grant. This signal driven by the VT82C585VPX to grant PCI access .com586A, or 586B south bridge. to the VT82C586, Request. PCI master requests for the PCI bus. Grant. Permission is given to the master to use the PCI bus.
Power and Ground
VDD VDD-CPU VDD-PCI VDD-DRAM GND 147, 165 10, 43, 61, 84 184, 201 97, 114 1, 15, 27, 38, 60, 83, 96, 119, 142, 164, 175, 183, 200 5V CPU PCI DRAM 0V I I I I I Power Supply for the internal logic of the VT82C585VPX chip (5v) Power Supply for the CPU Bus (3.3v or 5v) Power Supply for the PCI Bus (3.3v or 5v) Power Supply for the DRAM Bus (3.3v or 5v) Ground
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VT82C587VP Pinouts
VT82C580VPX
Figure 4. VT82C587VP Pin Diagram (Top View)
MD15 CMD5 MD31 MD7 MD23 MD14 MD30 MD6 MD22 MD13 GND MD29 MD5 VDD-DRAM GND MD21 MD4 MD20 MD12 MD28 MD3 GND MD19 MD11 MD27 MD2 MD18 VDD-DRAM MD10 MD26 IO I IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO HCLK GND CAS# RESET# DB32 HD0 HD1 HD2 HD3 GND VDD-CPU HD4 HD5 HD6 HD7 HD8 HD9 HD10 HD11 VDD-CPU 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 IO IO 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 I I I I IO IO IO IO IO IO IO IO IO IO IO IO 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
t4U.com
VT82C587VP Data Buffer
PQFP-100
IO IO IO IO IO IO IO IO IO IO IO IO
IO IO IO IO IO IO IO IO I I IO IO IO IO IO IO IO
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GND MD1 MD17 MD9 MD25 MD0 MD16 MD8 MD24 VDD GND MSTB# HSTB# PLINK0 PLINK1 PLINK2 PLINK3 PLINK4 PLINK5 PLINK6
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GND HD12 HD13 HD14 HD15 HD16 HD17 HD18 HD19 GND HD20 HD21 HD22 HD23 GND VDD-CPU HD24 HD25 HD26 HD27 HD28 HD29 HD30 HD31 CMD4 CMD3 CMD2 CMD1 CMD0 PLINK7
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
IO IO IO IO IO IO IO IO I I I I I IO
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Figure 5. VT82C587VP Pin List (Alphabetical Order)
Pin No. Pin Name 83 29 28 27 26 25 79 85 1 10 15 40 50 59 66 70 82 90 81 CAS# CMD0 CMD1 CMD2 CMD3 CMD4 CMD5 DB32 GND GND GND GND GND GND GND GND GND GND HCLK HD00 HD01 HD02 HD03 HD04 HD05 Pin No. Pin Name 94 95 96 97 98 99 2 3 4 5 6 7 8 9 11 12 13 14 17 18 19 20 21 22 23 HD06 HD07 HD08 HD09 HD10 HD11 HD12 HD13 HD14 HD15 HD16 HD17 HD18 HD19 HD20 HD21 HD22 HD23 HD24 HD25 HD26 HD28 HD29 HD30 Pin No. Pin Name 24 38 45 49 55 60 64 68 73 77 43 47 52 57 62 71 75 80 44 48 54 63 65 72 HD31 HSTB# MD00 MD01 MD02 MD03 MD04 MD05 MD06 MD07 MD08 MD09 MD10 MD11 MD12 MD13 MD14 MD15 MD16 MD17 MD18 MD20 MD21 MD22 Pin No. Pin Name 76 42 46 51 56 61 69 74 78 39 37 36 35 34 33 32 31 30 84 41 16 91 100 53 67 MD23 MD24 MD25 MD26 MD27 MD28 MD29 MD30 MD31 MSTB# PLINK0 PLINK1 PLINK2 PLINK3 PLINK4 PLINK5 PLINK6 PLINK7 RESET# VDD VDD-CPU VDD-CPU VDD-CPU VDD-DRAM VDD-DRAM
VT82C580VPX
t4U.com
86 87 88 89 92 93
DataShee
.com HD27 58 MD19
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Table 3. VT82C587VP Pin Descriptions
Signal Name HD[31:0] Pin No. 24-17, 14-11, 9-2, 99-92, 8986 Power CPU I/O Signal Description
VT82C580VPX
CPU Data Port
B Host CPU Data. These signals are connected to the CPU data bus. The CPU data bus is interleaved between the two VT82C587VP chips for every byte, effectively creating an even and odd 587VP.
DRAM Data Port
MD[31:0] 78, 74, 69, 61, 56, 51, 46, 42, 76, 72, 65, 63, 58, 54, 48, 44, 80, 75, 71, 62, 57, 52, 47, 43, 77, 73, 68, 64, 60, 55, 49, 45 DRAM B Memory Data. These signals are connected to the DRAM data bus. The DRAM data bus is interleaved between the two VT82C587VP for every byte, effectively creating an even and odd VT82C587VP.
VT82C585VPX Interface
DB32 CMD[5:0] 85 79, 25-29 DRAM DRAM I I
t4U.com
HSTB# MSTB# PLINK[7:0] 38 39 30-37 DRAM DRAM DRAM I I B
DRAM Width. This is used to control the width of the DRAM data bus Command. The buffers in the VT82C587VP are controlled by the VT82C585VPX through these command signals. The CMD5 input is used for UMA support only so may be tied high. The VT82C585VPX may be programmed to drive its CMD5 output high at all times for backwards DataShee compatibility with 82C585VP-based (non-VPX) designs. Host Data Strobe. .com Assertion causes data to be posted in the CPU read buffer Memory Strobe. Assertion causes data to be posted in the DRAM write buffer. PCI Link. These signals are connected to the PLINK data bus on the VT82C585VPX. This the data path between the VT82C585VPX and the VT82C587VP chips. Each VT82C587VP connects to one-byte of the 16bit bus.
Clock and Miscellaneous Control
HCLK RESET# CAS# 81 84 83 CPU CPU CPU I I I Host Clock. Primary clock input used to drive the part. Host Reset. Primary reset signal for the VT82C587VP.
DRAM CAS Synchronization. Connects to any DRAM CAS signal to synchronize the clocks with DRAM CAS. Required for Burst EDO DRAM operation only; can be tied high if BEDO DRAMs will never be used in the system design. It is recommended to maintain same skew among the eight DRAM CAS# lines for Burst EDO operation.
Power and Ground
VDD VDD-DRAM VDD-CPU GND 41 53, 67 16, 91, 100 1, 10, 15, 40, 50, 59, 66, 70, 79, 90 5V DRAM CPU 0V I I I I Power Supply for the Internal Logic of the chip (5v) Power Supply for the DRAM interface (3.3v or 5v) Power Supply for the CPU bus (3.3v or 5v). Ground
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VT82C580VPX
Offset 58 59 5A-5F 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E-6F DRAM Control DRAM Configuration 1 DRAM Configuration 2 DRAM Row Ending Address: Bank 0 Ending (HA[29:22]) Bank 1 Ending (HA[29:22]) Bank 2 Ending (HA[29:22]) Bank 3 Ending (HA[29:22]) Bank 4 Ending (HA[29:22]) Bank 5 Ending (HA[29:22]) DRAM Type Shadow RAM Control C0000-CFFFF Shadow RAM Control D0000-DFFFF Shadow RAM Control E0000-FFFFF DRAM Reference Timing DRAM Timing Control 1 DRAM Timing Control 2 32-Bit DRAM Width -reserved- (do not program) -reserved- (do not program) DRAM Refresh Counter DRAM Refresh Control SDRAM Control DRAM Control Drive Strength -reservedDefault 40 05 01 01 01 01 01 01 00 00 00 00 AB 00 00 00 00 00 00 00 00 00 00 Default 00 00 00 00 00 00 00 00 00 Acc RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW -- Acc DataShe RW RW WC RW RW RW RW RW --
REGISTERS
Register Overview
The following tables summarize the configuration and I/O registers of the VT82C585VPX. These tables also document the power-on default value ("Default") and access type ("Acc") for each register. Access type definitions used are RW (Read/Write), RO (Read/Only), "--" for reserved / used (essentially the same as RO), and RWC (or just WC) (Read / Write 1's to Clear individual bits). Registers indicated as RW may have some read/only bits that always read back a fixed value (usually 0 if unused); registers designated as RWC or WC may have some read-only or read write bits (see individual register descriptions for details). Detailed register descriptions are provided in the following section of this document. All offset and default values are shown in hexadecimal unless otherwise indicated
Table 4. VT82C585VPX Registers
Configuration Space VT82C585VPX Header Registers Offset t4U.com 1-0 3-2 5-4 7-6 8 9 A B C D E F 10-27 28-2F 30-33 34-3B 3C 3D 3E 3F PCI Configuration Space Header Vendor ID Device ID Command Status Revision ID Program Interface Sub Class Code Base Class Code -reserved- (cache line size) Latency Timer Header Type Built In Self Test (BIST) -reserved- (base address registers) -reserved- (unassigned) -reserved- (expan ROM base addr) -reserved- (unassigned) -reserved- (interrupt line) -reserved- (interrupt pin) -reserved- (minimum grant) -reserved- (maximum latency)
Default Acc 1106 RO Offset PCI Bus Control 0585 RO 70 PCI Buffer Control 0007 RW .comCPU to PCI Flow Control 1 71 02A0 WC 72 CPU to PCI Flow Control 2 nn RO 73 PCI Master Control 1 00 RO 74 PCI Master Control 2 00 RO 75 PCI Arbitration 1 06 RO 76 PCI Arbitration 2 00 -- 77 -reserved- (chip test - do not program) 00 RW 78-FF -reserved00 RO 00 RO 00 -- 00 -- 00 -- 00 -- 00 -- 00 -- 00 -- 00 --
e
Configuration Space VT82C585VPX-Specific Registers Offset 50 51 52 53 54 55 56 57 Cache Control Cache Control 1 Cache Control 2 Non-Cacheable Control System Performance Control Non-Cacheable Region #1 High Byte Non-Cacheable Region #1 Low Byte Non-Cacheable Region #2 High Byte Non-Cacheable Region #2 Low Byte Default 00 00 02 00 00 00 00 00 Acc RW RW RW RW RW RW RW RW
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Configuration Space I/O
Mechanism #1 These ports respond only to double-word accesses. Byte or word accesses will be passed on unchanged. Port CFB-CF8 - Configuration Address ......................... RW 31 Configuration Space Enable 0 Disabled .................................................default 1 Convert configuration data port writes to configuration cycles on the PCI bus ........................................ always reads 0 30-24 Reserved 23-16 PCI Bus Number Used to choose a specific PCI bus in the system 15-11 Device Number Used to choose a specific device in the system 10-8 Function Number Used to choose a specific function if the selected device supports multiple functions 7-2 Register Number Used to select a specific DWORD in the device's configuration space ........................................ always reads 0 1-0 Fixed
VT82C580VPX
t4U.com Port CFF-CFC - Configuration Data .............................. RW
DataShee
.com Refer to PCI Bus Specification Version 2.1 for further details on operation of the above configuration registers.
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Register Descriptions
PCI Configuration Space Header All registers are located in PCI configuration space. They should be programmed using PCI configuration mechanism 1 through CF8 / CFC. Offset 1-0 - Vendor ID .......................................................RO 15-0 ID Code (reads 1106h to identify VIA Technologies) Offset 3-2 - Device ID .........................................................RO 15-0 ID Code (reads 585h to identify the VT82C585VPX)
VT82C580VPX
Offset 5-4 - Command ....................................................... RW ........................................ always reads 0 15-10 Reserved 9 Fast Back-to-Back Cycle Enable ....................... RW 0 Fast back-to-back transactions only allowed to the same agent ........................................default 1 Fast back-to-back transactions allowed to different agents 8 SERR# Enable..................................................... RW 0 SERR# driver disabled ...........................default 1 SERR# driver enabled (SERR# is used to report parity errors if bit-6 is set). t4U.com 7 Address / Data Stepping ...................................... RO 0 Device never does stepping....................default Offset 8 .com - Revision ID ........................................................ RO 1 Device always does stepping 0-7 VT82C585VPX Chip Revision Code (00=First 6 Parity Error Response........................................ RW Silicon) 0 Ignore parity errors & continue ..............default 1 Take normal action on detected parity errors Offset 9 - Programming Interface .................................... RO 5 VGA Palette Snoop .............................................. RO This register is defined in different ways for each Base/Sub0 Treat palette accesses normally ..............default Class Code value and is undefined for this type of device. 1 Don't respond to palette accesses on PCI bus 0-7 Interface Identifier ........................... always reads 00 4 Memory Write and Invalidate Command.......... RO 0 Bus masters must use Mem Write ..........default Offset A - Sub Class Code ................................................. RO 1 Bus masters may generate Mem Write & Inval 0-7 Sub Class Code .......reads 00 to indicate Host Bridge 3 Special Cycle Monitoring .................................... RO 0 Does not monitor special cycles .............default Offset B - Base Class Code ................................................ RO 1 Monitors special cycles 0-7 Base Class Code .. reads 06 to indicate Bridge Device 2 Bus Master .......................................................... RO 0 Never behaves as a bus master Offset D - Latency Timer ................................................. RW 1 Can behave as a bus master ....................default Specifies the latency timer value in PCI bus clocks. Bits 0-2 1 Memory Space...................................................... RO are fixed, resulting in a granularity of 8 clocks. 0 Does not respond to memory space 7-3 Guaranteed Time Slice for CPU................default=0 1 Responds to memory space ....................default ........................................ always reads 0 2-0 Reserved 0 I/O Space .......................................................... RO 0 Does not respond to I/O space Offset E - Header Type ..................................................... RO 1 Responds to I/O space ............................default 0-7 Header Type Code............ reads 00: single function
Offset 7-6 - Status .......................................................... RWC 15 Detected Parity Error 0 No parity error detected......................... default 1 Error detected. May be set even if error response is disabled (command register bit-6).. ....................................write one to clear 14 Signaled System Error ....................... always reads 0 1 SERR# asserted 13 Signaled Master Abort....................... always reads 0 1 Transaction aborted by the master 12 Received Target Abort 0 No abort received .................................. default 1 Transaction aborted by the target...................... ....................................... write 1 to clear 11 Signaled Target Abort........................ always reads 0 0 Target Abort never signaled 10-9 DEVSEL# Timing 00 Fast 01 Medium....................................always reads 01 10 Slow 11 Reserved 8 Data Parity Error Detected ...............always reads 0 7 Fast Back-to-Back Capable ...............always reads 1 ........................................ always reads 0 6 Reserved 5 66MHz Capable ..................................always reads 1 ........................................ always reads 0 DataShee 4-0 Reserved
Offset F - Built In Self Test (BIST) .................................. RO 7 BIST Supported...... reads 0: no supported functions 6 Start Test .......... write 1 to start but writes ignored ........................................ always reads 0 5-4 Reserved 3-0 Response Code ..........0 = test completed successfully
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Preliminary Revision 0.1 January 9, 1997 -16Register Descriptions
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VT82C585VPX-Specific Configuration Registers Cache Control
VT82C580VPX
Offset 51 - Cache Control 2 ............................................. RW ........................................RW, default=0 7-6 Reserved 5 Backoff CPU Used when register 52h bit-2 is set for "L2 fill when CACHE# is inactive". This bit should normally be set to 0 for best performance, but performance differences are typically not significantly noticable at a system level. 0 Defer ready return until L2 is filled ....... default 1 Backoff CPU until L2 is filled ........................................RW, default=0 4 Reserved 3 SRAM Banks 0 1 Bank.................................................... default 1 2 Banks ........................................RW, default=0 2 Reserved 1-0 Cache Size 00 256K .................................................... default 01 512K 10 1M 11 2M
Offset 50- Cache Control 1 ............................................... RW 7-6 Cache Enable 00 Cache disable .........................................default 01 Cache Init - always does L2 fill 10 Cache enable (normal operation) 11 -reserved- (do not program) 5 Linear Burst Enable 0 Disable ...................................................default 1 Enable 4-3 Tag Configuration 00 8+0 - 8 Tag bits, no alt (dirty) bit...........default 01 7+1 - 7 Tag bits + alternate (dirty) bit 10 10 - 10 Tag bits, no alt (dirty) bit 11 9+1 - 9 Tag bits + alternate (dirty) bit 2 SDRAM Interface Select Selects the function of pins 90-93 and 73-76: 0 CWE[0-7]#.............................................default 1 GWE#, BWE#, SCASx#, SRASx#, SWEx# 1-0 SRAM Type 00 No SRAM...............................................default 01 Reserved t4U.com 10 Burst SRAM 11 Pipeline Burst SRAM .com
DataShee
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Offset 52 - Non-Cacheable Control.................................. RW 7 C0000-C7FFF Cacheable & Write-Protect ... def=0 6 D0000-DFFFF Cacheable & Write-Protect ... def=0 5 E0000-EFFFF Cacheable & Write-Protect ... def=0 4 F0000-FFFFF Cacheable & Write-Protect.... def=0 3 Reserved (no function)....................... RW, default=0 2 L2 Fill 0 Normal L2 cache fill...............................default 1 Force the requested data to be filled into the L2 cache (provided that L2 cache is enabled), even if the CPU does a read cycle with CACHE# de-asserted. Setting this bit significantly improves performance. 1 Reserved (no function)....................... RW, default=0 0 L2 Write Thru/Write-Back 0 Write-Back ............................................default 1 Write-Thru
VT82C580VPX
Offset 54 - Non-Cacheable Region #1 High Byte ........... RW 15-8 Base Address MSBs - A<28:21> ................default=0 As noted below, the base address must be a multiple of the region size. Offset 55 - Non-Cacheable Region #1 Low Byte ............ RW 7-3 Base Address LSBs - A<20:16> .................default=0 As noted below, the base address must be a multiple of the region size. 2-0 Range (Region Size) 000 Disable................................................... default 001 64K 010 128K (Base Address A16 must be 0) 011 256K (Base Address A16-17 must be 0) 100 512K (Base Address A16-18 must be 0) 101 1M (Base Address A16-19 must be 0) 110 2M (Base Address A16-20 must be 0) 111 4M (Base Address A16-21 must be 0)
Offset 53 - System Performance Control......................... RW Offset 56 - Non-Cacheable Region #2 High Byte ........... RW 7 Read Around Write 15-8 Base Address MSBs - A<28:21> ................ default=0 0 Disable ...................................................default As noted below, the base address must be a multiple 1 Enable of the region size. 6 Cache Read Pipeline Cycle 0 Disable ...................................................default Offset 57 - Non-Cacheable Region #2 Low Byte ............ RW 1 Enable 7-3 Base Address LSBs - A<20:16> .................default=0 5 Cache Write Pipeline Cycle t4U.com As noted below, the base address must be a multiple DataShee 0 Disable ...................................................default of the region size. 1 Enable .com 2-0 Range (Region Size) 4 DRAM Pipeline Cycle 000 Disable................................................... default 0 Disable ...................................................default 001 64K 1 Enable 010 128K (Base Address A16 must be 0) 3 PCI Master Peer Concurrency 011 256K (Base Address A16-17 must be 0) 0 Disable ...................................................default 100 512K (Base Address A16-18 must be 0) 1 Enable 101 1M (Base Address A16-19 must be 0) ........................................ RW, default=0 2-0 Reserved 110 2M (Base Address A16-20 must be 0) 111 4M (Base Address A16-21 must be 0)
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Preliminary Revision 0.1 January 9, 1997 -18Register Descriptions
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DRAM Control These registers are normally set at system initialization time and not accessed after that during normal system operation. Some of these registers, however, may need to be programmed using specific sequences during power-up initialization to properly detect the type and size of installed memory (refer to the VIA Technologies 82C580 BIOS porting guide for details).
VT82C580VPX
Offset 59 - DRAM Configuration 2 ................................. RW 7-5 Bank 4/5 MA Map Type (EDO/FPG) 000 8-bit Column Address............................ default 001 9-bit Column Address 010 10-bit Column Address 011 11-bit Column Address 100 12-bit Column Address 101 Reserved 11x Reserved Bank 4/5 MA Map Type (SDRAM) 0xx 16Mbit SDRAM .................................... default 1xx 64Mbit SDRAM ........................................RW, default=0 4-3 Reserved 2-0 Last Bank DRAM Populated 000 Bank 0 001 Bank 1 010 Bank 2 011 Bank 3 100 Bank 4 101 Bank 5.................................................... default 11x Reserved Offset 5A-5F - DRAM Row Ending Address: All of the registers in this group default to 01h: Offset 5A - Bank 0 Ending (HA[29:22]) ....................... RW
Table 5. System Memory Map
Space Start DOS 0 VGA 640K BIOS 768K BIOS 784K BIOS 800K BIOS 816K BIOS 832K BIOS 848K BIOS 864K BIOS 880K BIOS 896K BIOS 960K Sys 1MB t4U.com Bus D Top Init 4G-64K Size 640K 128K 16K 16K 16K 16K 16K 16K 16K 16K 64K 64K -- Address Range 00000000-0009FFFF 000A0000-000BFFFF 000C0000-000C3FFF 000C4000-000C7FFF 000C8000-000CBFFF 000CC000-000CFFFF 000D0000-000D3FFF 000D4000-000D7FFF 000D8000-000DBFFF 000DC000-000DFFFF 000E0000-000EFFFF 000F0000-000FFFFF 00100000-DRAM Top DRAM Top-FFFEFFFF 64K FFFEFFFF-FFFFFFFF Comment Cacheable Used for SMM Shadow Ctrl 1 Shadow Ctrl 1 Shadow Ctrl 1 Shadow Ctrl 1 Shadow Ctrl 2 Shadow Ctrl 2 Shadow Ctrl 2 Shadow Ctrl 2 Shadow Ctrl 3 Shadow Ctrl 3 Can have hole
DataShee
000Fxxxx alias Offset 5B - Bank 1 Ending (HA[29:22]) ....................... RW .com Offset 58 - DRAM Configuration 1 ................................. RW Offset 5C - Bank 2 Ending (HA[29:22]) ...................... RW 7-5 Bank 0/1 MA Map Type (EDO/FPG) 000 8-bit Column Address Offset 5D - Bank 3 Ending (HA[29:22]) ...................... RW 001 9-bit Column Address 010 10-bit Column Address ..........................default Offset 5E - Bank 4 Ending (HA[29:22]) ....................... RW 011 11-bit Column Address Offset 5F - Bank 5 Ending (HA[29:22]) ....................... RW 100 12-bit Column Address 101 Reserved Note : BIOS is required to fill the ending address registers 11x Reserved for all banks even if no memory is populated. The endings have to be in incremental order. Bank 0/1 MA Map Type (SDRAM) 0xx 16Mbit SDRAM.....................................default Offset 60 - DRAM Type ................................................... RW 1xx 64Mbit SDRAM ........................................ always reads 0 7-6 Reserved ........................................ RW, default=0 4 Reserved 5-4 DRAM Type for Bank 4/5 00 Fast Page Mode DRAM (FPG).............. default 3-1 Bank 2/3 MA Map Type (EDO/FPG) 01 EDO DRAM (EDO) 000 8-bit Column Address ............................default 10 Reserved 001 9-bit Column Address 11 Synchronous DRAM (SDRAM) 010 10-bit Column Address 3-2 DRAM Type for Bank 2/3.....................default=FPG 011 11-bit Column Address 1-0 DRAM Type for Bank 0/1.....................default=FPG 100 12-bit Column Address 101 Reserved 11x Reserved Bank 2/3 MA Map Type (SDRAM) 0xx 16Mbit SDRAM.....................................default 1xx 64Mbit SDRAM ........................................ RW, default=0 0 Reserved
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Preliminary Revision 0.1 January 9, 1997 -19Register Descriptions
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Offset 61 - Shadow RAM Control 1................................. RW 7-6 CC000h-CFFFFh 00 Read/write disable ..................................default 01 Write enable 10 Read enable 11 Read/write enable 5-4 C8000h-CBFFFh 00 Read/write disable ..................................default 01 Write enable 10 Read enable 11 Read/write enable 3-2 C4000h-C7FFFh 00 Read/write disable ..................................default 01 Write enable 10 Read enable 11 Read/write enable 1-0 C0000h-C3FFFh 00 Read/write disable ..................................default 01 Write enable 10 Read enable 11 Read/write enable
VT82C580VPX
Offset 63 - Shadow RAM Control 3 ................................ RW 7-6 E0000h-EFFFFh 00 Read/write disable ................................. default 01 Write enable 10 Read enable 11 Read/write enable 5-4 F0000h-FFFFFh 00 Read/write disable ................................. default 01 Write enable 10 Read enable 11 Read/write enable 3-2 Memory Hole 00 None .................................................... default 01 512K-640K 10 15M-16M (1M) 11 14M-16M (2M) 1 SMI Redirect to A0000h-BFFFFh 0 Disable Redirection ............................... default 1 Enable Redirection 0 DRAM A0000h-BFFFFh Access 0 Disable read write to A0000-B0000 ...... default 1 Enable read write to A0000-B0000 in DRAM Offset 62 - Shadow RAM Control 2................................. RW Note: A0000-BFFFF is reserved for use by VGA 7-6 DC000h-DFFFFh controllers for system access to the VGA frame 00 Read/write disable ..................................default buffer. Setting this bit directs accesses to Axxxx01 Write enable Bxxxx to corresponding memory addresses in system t4U.com DataShee 10 Read enable DRAM instead of directing those accesses to the PCI 11 Read/write enable .com bus for VGA frame buffer access. 5-4 D8000h-DBFFFh 00 Read/write disable ..................................default 01 Write enable 10 Read enable 11 Read/write enable 3-2 D4000h-D7FFFh 00 Read/write disable ..................................default 01 Write enable 10 Read enable 11 Read/write enable 1-0 D0000h-D3FFFh 00 Read/write disable ..................................default 01 Write enable 10 Read enable 11 Read/write enable
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Preliminary Revision 0.1 January 9, 1997 -20Register Descriptions
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9,$7HFKQRORJLHV,QF
Offset 64 - DRAM Reference Timing (FPG Only) ......... RW Defines basic timing for Fast Page (FPG) DRAMs. Timing for banks populated with EDO / SDRAM is defined per Rx65-66.
VT82C580VPX
Offset 66 - DRAM Timing Control 2 (EDO/SDRAM)... RW 7 EDO Test Mode Enable 0 Normal Mode......................................... default 1 EDO Test Mode 7-6 RAS Precharge Time ........................................ always reads 0 6 Reserved 00 2T 5 SDRAM CAS Latency................................default=0 01 3T The definition of this bit is the same as Rx6C bit-3 for 10 4T .....................................................default backwards compatibility with Apollo VP 11 6T (VT82C585VP). The two bits are OR'd: if either bit 5-4 RAS Pulse Width is set to one, a latency of 3 is selected; if both bits are 00 3T 0 a latency of 2 is selected. 01 4T ........................................ always reads 0 4 Reserved 10 5T .....................................................default 3 Turbo EDO Mode Enable (recommended setting=0) 11 6T 0 -2-2-2 Two-Cycle Burst............................... def 3-2 CAS Read Pulse Width 1 -1-1-1 One-Cycle Burst (only applicable to 00 1T turbo EDO DRAMs) 01 2T (FPG), 1T (EDO) 2 MD to HD FIFO Control . (recommended setting=0) 10 3T (FPG), 2T (EDO)..............................default 0 -1-1-1 to pop the data from the DRAM-to-CPU 11 4T (FPG), 3T (EDO) FIFO to the CPU.................................... default 1 CAS Write Pulse Width 1 -2-2-2 to pop data from the FIFO to the CPU 0 1T 1 SDRAM RAS-Precharge Reduction 1 2T .....................................................default ...................... (recommended setting=0) 0 Column Address to CAS Delay (see also Rx67[7]) 0 Use Rx64[7-6] for RAS-Precharge time ...... def 0 1T 1 Reduce the above by 1T for SDRAM access 1 2T .....................................................default 0 SDRAM RAS-to-CAS Delay Reduction .................. ...................... (recommended setting=1) ataShee t4U.com Offset 65 - DRAM Timing Control 1 (EDO/SDRAM) ... RW D 0 Use Rx64[0] for Column Address to CAS 7-6 Page Mode Control delay for SDRAM) ................................ default 00 Page closes after access..........................default .com 1 Column Address to CAS delay is fixed at 1T 01 Reserved for SDRAM 10 Page stays open after access 11 Page closes if CPU is idle Offset 67 - 32-Bit DRAM Width ...................................... RW 5 Fast DRAM Decoding Enable 7 RAS to Column Address Delay 0 End of Second T2...................................default This bit determines the number of CPU clocks from 1 End of First T2 (recommended setting) RAS assertion to column address assertion. Determines the latch point for all DRAM-related 0 1T (recommended setting) ..................... default decoding (bank, page-hit, MA address mux setup, 1 2T (only set this with heavily loaded DRAM) etc). DRAM control signals (RAS#, CAS#, or 6 NA# Delay SDRAM commands) are also activated at this point. 0 No NA# delay, 3-1-1-1-2-1-1-1 for L2 cache 4 EDO DRAM Leadoff Cycle Reduction read hit (recommended setting) ............. default 0 Normal leadoff cycle (recommended) ....default 1 Delay NA# 1T, 3-1-1-1-3-1-1-1 1 Reduce leadoff cycle by 1T This bit only applies when 2 banks of PBSRAM is 3 DRAM Data Latch Delay .(recommended setting=0) installed. 0 Latch DRAM data 1 cycle before CPU ....... def 5 Bank 5 Width. 1=32-bit, 0= 64 bit...........default=64 1 Latch DRAM Data 1/2 cycle before the CPU 4 Bank 4 Width. 1=32-bit, 0= 64 bit ..........default=64 2 Pin 88 Function Select 3 Bank 3 Width. 1=32-bit, 0= 64 bit ..........default=64 0 DB32 .....................................................default 2 Bank 2 Width. 1=32-bit, 0= 64 bit ..........default=64 1 TA9 1 Bank 1 Width. 1=32-bit, 0 =64 bit ..........default=64 ........................................ RW, default=0 1 Reserved 0 Bank 0 Width. 1=32-bit, 0= 64 bit ..........default=64 0 Relaxed DRAM Read Cycle Latency ....... default=0 Used to relax the timing when Rx53[7] (read-aroundwrite) and Rx65[5] (fast decoding) are both enabled. 0 No effect (DRAM decoding time is end of T2) 1 Add 1 cycle delay (DRAM decoding time is the end of the second T2) if the write-buffer is not empty (recommended setting).
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Preliminary Revision 0.1 January 9, 1997 -21Register Descriptions
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Offset 68 - Reserved (Do Not Program) .......................... RW 7-4 Reserved (do not program)................ RW, default = 0 3 Pin 126 Function Select 0 Pin 126 remains high all the time (for backwards compatibility with VT82C585VPbased designs that drive the VT82C587VP "CMD5" input with pin 126)..................default 1 Pin 126 is MA12 for 64Mb DRAM support 2-0 Reserved (do not program)................ RW, default = 0
VT82C580VPX
Offset 6C - SDRAM Control............................................ RW 7 64Mbit SDRAM Interleave 0 2-bank interleave for 64Mbit SDRAM .. default 1 4-bank interleave for 64Mbit SDRAM Note: This bit is a don't-care for 16Mbit SDRAM 6 SDRAM Burst Write 0 Disabled................................................. default 1 Enabled 5 SDRAM Bank Interleave Enable 0 Disabled (bit-7 is a don't care) .............. default Offset 69 - Reserved (Do Not Program) .......................... RW 1 Enabled 7-0 Reserved (do not program)................ RW, default = 0 16Mbit is 2-way only 64Mbit is defined by bit-7 of this register .......................................RW, default= 0 4 Reserved 3 SDRAM CAS Latency (see also Rx66[5]) 0 Cycle latency is 2 (RX66[5] must be 0). default 1 Cycle latency is 3 Offset 6A - Refresh Counter ............................................. RW 2-0 SDRAM Operation Mode Select 7-0 Refresh Counter (in units of 16 CPUCLKs) .... def=0 000 Normal SDRAM Mode.......................... default note: When set to 00, DRAM refresh is disabled 001 NOP Command Enable 010 All-Banks-Precharge Command Enable. Offset 6B - Refresh Control .............................................. RW CPU-to-DRAM cycles are converted 7 CBR (CAS-before-RAS) Refresh to All-Banks-Precharge commands. 0 Disable CBR Refresh .............................default 011 CPU-to-DRAM cycles are converted to 1 Enable CBR Refresh commands and the commands are driven on 6 Burst Refresh (Burst 4 Times) MA[11:0]. The BIOS selects an appropriate ataShee t4U.com 0 Disable burst refresh...............................default D host address for each row of memory such that 1 Enable burst refresh the right commands are generated on .com ........................................ RW, default=0 5-3 Reserved MA[11:0]. 2 Extended Timing 100 CBR Cycle Enable 0 Normal Timing.......................................default 101 Reserved 1 Force 2T from MA to RAS# and CAS# falling 11x Reserved for all cases (use this setting for heavily loaded DRAM and direct drive) Offset 6D - DRAM Control Drive Strength.................... RW ..........................................always read 0 1-0 Reserved 7 Bank Decoding Test....................................default=0 6 MA[0:1] Drive 0 12mA .................................................... default 1 24mA 5 Duplicate Copy of MA[0:1] Pin N17 Pin M17 Drive Control 0 RAS5# RAS4# bit 0 ........... default 1 MA1 MA0 bit 6 4 Force SMM Mode ......................................default=0 3 SDRAM Command Drive (SRAS#, SCAS#, SWE#) 0 12mA .................................................... default 1 24mA 2 MA[2:13] / WE# Drive 0 12mA .................................................... default 1 24mA 1 CAS# Drive 0 8 mA .................................................... default 1 12 mA 0 RAS# Drive 0 12mA .................................................... default 1 24mA
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Preliminary Revision 0.1 January 9, 1997 -22Register Descriptions
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PCI Bus Control These registers are normally programmed once at system initialization time. Offset 70 - PCI Buffer Control ......................................... RW 7 CPU to PCI Post-Write 0 Disabled .................................................default 1 Enabled 6 PCI Master to DRAM Post-Write 0 Disabled .................................................default 1 Enabled 5 PCI Master to DRAM Prefetch 0 Disabled .................................................default 1 Enabled ....................................... RW, default= 0 4 Reserved ........................................ always reads 0 3-2 Reserved 1 PCI Retry for CPU QW Access 0 Disabled .................................................default 1 Enabled 0 PCI Master Does Not Flush CPU to PCI Buffer 0 Master flushes CPU-to-PCI buffer .........default 1 Master does not flush CPU to PCI buffer
VT82C580VPX
Offset 72 - CPU to PCI Flow Control 2 ....................... RWC 7 Retry Status over 16 / 64 Times 0 No retry occurred................................... default 1 Retry occurred .......................... write 1 to clear 6 Retry Timeout Action 0 Retry Forever (record status only) ......... default 1 Flush buffer or return FFFFFFFF for read 5-4 Retry Count and Retry Backoff 00 Retry 2 times, back off CPU .................. default 01 Retry 16 times 10 Retry 4 times, back off CPU 11 Retry 64 times 3 Clear Failed Data and Continue Retry 0 Disabled................................................. default 1 When data is posting and retry fails, pop the failed data if any, and keep posting 2 CPU Backoff on PCI Read Retry Failure 0 Disabled................................................. default 1 Backoff CPU when reading data from PCI and retry fails 1 Reduce 1T for FRAME# Generation 0 Disabled................................................. default 1 Enabled 0 Reduce 1T for CPU Read PCI Slave 0 Disabled................................................. default 1 Enabled (bypass TRDY# to LRDY#)
Offset 71 - CPU to PCI Flow Control 1 ........................... RW 7 Dynamic Burst t4U.com 0 Disabled .................................................default 1 Enabled (see note under bit-3 below) .com 6 Byte Merge 0 Disabled .................................................default 1 Enabled ........................................ always reads 0 5 Reserved 4 PCI I/O Cycle Post Write 0 Disabled .................................................default 1 Enabled 3 PCI Burst 0 Disabled .................................................default 1 Enabled (bit7=1 will override this option) bit-7 bit-3 Operation 0 0 Every write goes into the write buffer and no PCI burst operations occur. 0 1 If the write transaction is a burst transaction, the information goes into the write buffer and burst transfers are later performed on the PCI bus. If the transaction is not a burst, PCI write occurs immediately (after a write buffer flush). 1 x Every write transaction goes to the write buffer; burstable transactions will then burst on the PCI bus and non-burstable won't. This is the normal setting. 2 Enable PCI Fast Back-to-Back Write .. def=0 (disa) 1 Enable Quick Frame Generation... def=0 (disabled) 0 Enable 1 Wait State PCI Cycles .... def=0 (disabled)
DataShee
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Offset 73 - PCI Master Control 1..................................... RW 7 Local Memory Decoding 0 Fast (address phase) ...............................default 1 Slow (first data phase) 6 PCI Master 1-Wait-State Write 0 Zero wait state TRDY# response ...........default 1 One wait state TRDY# response 5 PCI Master 1-Wait-State Read 0 Zero wait state TRDY# response ...........default 1 One wait state TRDY# response ........................................ always reads 0 4 Reserved 3 Assert STOP# after PCI Master Write Timeout 0 Disabled .................................................default 1 Enabled 2 Assert STOP# after PCI Master Read Timeout 0 Disabled .................................................default 1 Enabled 1 LOCK# Function 0 Disabled .................................................default 1 Enabled 0 PCI Master Broken Timer Enable 0 Disabled .................................................default 1 Enabled. Force into arbitration when there is no FRAME# 16 PCICLK's after the GRANT.
VT82C580VPX
Offset 75 - PCI Arbitration 1 ........................................... RW 7 Arbitration Mechanism 0 PCI has priority...................................... default 1 Fair arbitration between PCI and CPU 6 Arbitration Mode 0 REQ-based (arbitrate at end of REQ#) .. default 1 Frame-based (arbitrate at end of each FRAME#) ........................................RW, default=0 5-4 Reserved 3-0 PCI Master Bus Time-Out (force into arbitration after a period of time) 0000 Disable................................................... default 0001 1x32 PCICLKs 0010 2x32 PCICLKs ... ... 1111 15x32 PCICLKs
Offset 76 - PCI Arbitration 2 ........................................... RW 7 Master Priority Rotation Enable 0 Disable (arbitration per Rx75 bit-7)....... default 1 Enable (arbitration per bits 5-4 of this register) (gives the CPU higher priority than either of the mechanisms defined by Rx75 bit-7) ........................................ always reads 0 6 Reserved 5-4 Master Priority Rotation Control Offset 74 - PCI Master Control 2..................................... RW 00 Disabled (arbitration per Rx75 bit-7)..... default t4U.com DataShee 7 PCI Enhance Command Support 01 Grant to CPU after every PCI master grant 0 Disabled .................................................default .com 10 Grant to CPU after every 2 PCI master grants 1 Enabled 11 Grant to CPU after every 3 PCI master grants 6 PCI Master Single Write Merge With setting 01, the CPU will always be granted 0 Disabled ................................................default access after the current bus master completes, no 1 Enabled matter how many PCI masters are requesting. With ........................................ always reads 0 5-0 Reserved setting 10, if other PCI masters are requesting during the current PCI master grant, the highest priority master will get the bus after the current master completes, but the CPU will be guaranteed to get the bus after that master completes. With setting 11, if other PCI masters are requesting, the highest priority will get the bus next, then the next highest priority will get the bus, then the CPU will get the bus. In other words, with the above settings, even if multiple PCI masters are continuously requesting the bus, the CPU is guaranteed to get access after every master grant (01), after every other master grant (10) or after every third master grant (11). ........................................ always reads 0 3-1 Reserved ........................................RW, default=0 0 Reserved
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VT82C580VPX
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings Parameter
Ambient operating temperature Storage temperature Input voltage Output voltage (VDD = 3.1 - 3.6V)
Min
0 -55 -0.5 -0.5
Max
70 125 5.5 VDD + 0.5
Unit
oC oC Volts Volts
Note: Stress above the conditions listed may cause permanent damage to the device. Functional operation of this device should be restricted to the conditions described under operating conditions.
DC Characteristics
TA-0-70oC, VDD=5V+/-5%, GND=0V
t4U.com
Symbol
VIL VIH VOL VOH IIL IOZ ICC
Parameter
Input low voltage Input high voltage Output low voltage Output high voltage Input leakage current Tristate leakage current Power supply current
Min
2.0 2.4 -
Max
VDD+0.5 0.45 +/-10 +/-20
Unit
V V V V uA uA mA
Condition
DataShee
.com -0.50 0.8
IOL=4.0mA IOH=-1.0mA 0.com
Preliminary Revision 0.1 January 9, 1997 -25Electrical Specifications
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AC Timing Specifications
VT82C580VPX
AC timing specifications provided are based on external zero-pf capacitance load. Min/max cases are based on the following table:
Table 6. AC Timing Min / Max Conditions
Min VDD-CPU, VDD-PCI, VDD-DRAM VDD Temperature 5.25 5.25 0 Max 3.135 4.75 70
Pad load derating curve specifications are listed from 0pf to 80pf with 5pf resolution; above 80 pf use 20 pf resolution up to 200 pf. The following pads are provided:
Table 7. PAD Load Derating Curve (I/V curve)
External pad name vpad000 vpad 001 vpad 002 vpad 005 vpad 007 Voltage 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 24mA 12mA 12mA 8mA Remark
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vpad 009 vpad 011 vpad 012 .com vpad 013 vpad 014
DataShee
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Table 8. AC Characteristics - CPU Cycle Timing
Parameter
ADS# Setup Time to CCLK Rising WR# Setup Time to CCLK Rising MIO# Setup Time to CCLK Rising DC# Setup Time to CCLK Rising BE[7:9[# Setup Time to CCLK Rising HITM# Setup Time to CCLK Rising CACHE# Setup Time to CCLK Rising HA[31:3] Setup Time to CCLK Rising ADS#,HITM#,WR#,MIO#,DC#,BE[7:0]#,CACHE# Hold Time from CCLK Rising HA[31:3] Hold Time from CCLK Rising BRDY# Valid Delay From CCLK Rising NA# Valid Delay From CCLK Rising AHOLD Valid Delay From CCLK Rising BOFF# Valid Delay From CCLK Rising EADS# Valid Delay From CCLK Rising KEN#/INV# Valid Delay from CCLK Rising BE[7:0]# Valid Delay from CCLK Rising HA[31:3] Valid Delay from CCLK Rising HA[31:3] Float Delay from CCLK Rising
VT82C580VPX
Min
5 5 5 5 5 5 5 5 2 2 3 3 3 3 3 3 4 4 4
Max
Pad
Notes
8 7 7 7 7 7 9 13 9
vpad000 vpad000 vpad000 vpad000 vpad000 vpad000 vpad002 vpad002
0 pf 0 pf 0 pf 0 pf 0 pf 0 pf 0 pf 0 pf 0 pf
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Preliminary Revision 0.1 January 9, 1997 -27Electrical Specifications
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Table 9. AC Characteristics - L2 Cache Timing
Parameter
COE# Valid Delay from CCLK Rising TA[9:0] Valid Delay from CCLK Rising TA[9:0] setup time to CCLK Rising TA[9:0] Hold Time from CCLK Rising TAGWE# Valid Delay from CCLK Rising CWE[7:0]#/GWE#/BWE# Active Delay from CCLK Rising CCS#(CALE) Valid Delay from CCLK Rising CADS# Valid Delay from CCLK Rising CADV# Valid Delay from CCLK Rising
VT82C580VPX
Min
2 3 8 1 2 2 2 2 2
Max
6 9
Pad
vpad000 vpad001
Notes
0 pf 0 pf
6 6 6 6 6
vpad000 vpad000 vpad000 vpad000 vpad000
0 pf 0 pf 0 pf 0 pf 0 pf
Table 10. AC Characteristics - DRAM Interface Timing
Parameter
RAS[5:0] Valid Delay from CCLK Rising CAS[7:0]# Valid Delay from CCLK Rising (EDO) DQM[7:0]# Valid Delay from CCLK Rising (SDRAM) SRAS# Valid Delay from CCLK Rising SCAS# Valid Delay from CCLK Rising SWE#,SWEB# Valid Delay from CCLK Rising MA[11:2]# Valid Delay from CCLK Rising on first Clock after RAS# asserts
Min
4 3 3 3 3 3 4 4 4 6
Max
9 8 7 7 7 7 9 10 10 15
Pad
vpad005 vpad007 vpad011 vpad005 vpad005 vpad005 vpad005 vpad005 vpad005 vpad005
Notes
0 pf 0 pf
startpage 0 pf 0 pf Leadoff, 0pf 0 pf
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MA[1:0] Valid Delay from CCLK Rising (burst) MA[11:0] Flow Through Delay from HA for first read cycle MWE# Valid Delay from CCLK Rising
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Preliminary Revision 0.1 January 9, 1997 -28Electrical Specifications
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Table 11. AC Characteristics - PCI Cycle Timing
Parameter
AD[31:0] Valid Delay from PCLK Rising (address phase) AD[31:0] Valid Delay from PCLK Rising (data phase) AD[31:0] Setup Time to PCLK AD[31:0] Hold Time CBE[3:0]#,FRAME#,TRDY#,IRDY#,STOP#,DEVSEL# Valid Delay from PCLK Rising CBE[3:0]#,FRAME#,TRDY#,IRDY#,STOP#,DEVSEL# Float Delay from CCLK Rising CBE[3:0]#,FRAME#,TRDY#,IRDY#,STOP#,DEVSEL# Setup Time to CCLK Rising CBE[3:0]#,FRAME#,TRDY#,IRDY#,STOP#,DEVSEL# Hold Time from CCLK Rising PHLD#,REQ[3:0]# Setup Time to PCLK Rising GNT[3:0]#,PGNT# Valid Delay from PCLK Rising 7 2 7 2 6
VT82C580VPX
Min
5 5 7 2 3
Max
12 11
Pad
vpad012
Notes
0 pf
8 10
vpad013
0 pf
Table 12. AC Characteristics - Data Timing
Parameter HD Valid Delay from CCLK Rising HD Setup Time to CCLK Rising HD Hold Time from CCLK Rising MD Valid Delay from CCLK Rising (SDRAM) Min 3 2 2 3 4 8 14 vpad001 0 pf Max 7 Fig. vpad001 Notes 0 pf
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MD Valid Delay from CCLK Falling (EDO/FP) MD Setup Time to CCLK Rising (SDRAM) MD Setup Time to CCLK Falling (EDO) MD Hold Time from CCLK Rising (SDRAM) MD Hold Time from CCLK Falling (EDO)
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2 2 3 3
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Preliminary Revision 0.1 January 9, 1997 -29Electrical Specifications
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&&/. $'6 1$ &$
VT82C580VPX
%5'< :5 0$ 5$6 &$6
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0:( &' 0'
Figure 6. DRAM READ PIPE LINE EDO 5-2-2-2, 3-2-2-2
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&&/. $'6 1$ &$ %5'< :5 0$ 5$6 &$6 0 :( &' 0'
VT82C580VPX
Figure 7. POST WRITE 3111,DRAM EDO 2222
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&& /. $'6 %5'< :5 .(1 1$ & $ > @ % ( > @ & ' > @ & ' > @ 0 ' > @ 0 ' > @ 65$6 6&$6 6: ( ' 4 0 > @ 0: ( 0 $ > @ 0 $ > @ 0 $ > @ & 6 > @ & 6 > @
VT82C580VPX
Figure 8. SDRAM READ CYCLE (BANK INTERLEAVE, CAS LATENCY=3)
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VT82C580VPX
Figure 9. SDRAM WRITE CYCLE (BANK INTERLEAVE)
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& & /. :5 $'6 1$ %5'< &$ %( $'9 $'6& &( &2( 7$*: ( 7$ &'
VT82C580VPX
Figure 10. CPU READ HIT SYNCHRONOUS SRAM 3111
Preliminary Revision 0.1 January 9, 1997 -34Electrical Specifications
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& & /. :5 $'6 1$ %5'< &$ %(
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VT82C580VPX
$'9 $'6& &( *:( %:( &2( 7$*: ( 7$ &'
Figure 11. CPU WRITE HIT SYNCHRONOUS SRAM 3111
Preliminary Revision 0.1 January 9, 1997 -35Electrical Specifications
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VT82C580VPX
Figure 12. CPU READ MISS FILL SYNCHRONOUS SRAM
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&$
%( $'9 $'6& &( *: ( %: ( &2(
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7$*: (
7$
5$6
&$6
0: (
&'
0'
Figure 13. CPU READ MISS DIRTY L2 WRITE BACK FILL
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Electrical Specifications
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%(
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)5$0 ( '(96(/
$'
&%( ,5'<
75'<
Figure 14. CPU READ PCI SLAVE
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Electrical Specifications
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& & /. :5 $'6 1$ %5'< &$ %( &' 3 & /. )5$0( ' ( 9 6 ( / $' &%( ,5 ' < 75'<
VT82C580VPX
Figure 15. CPU WRITE PCI SLAVE WRITE BUFFER ON FAST BACK TO BACK
Preliminary Revision 0.1 January 9, 1997 -39Electrical Specifications
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& & /. :5 $'6 ($'6 %5'< &$
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%( + ,7 0 $+ 2 /'
%2))
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&' 0' 0$ 5$6 &$6 0:( 3& /. )5$0 ( ' (96(/ $' &%(
,5 ' < 75 ' <
Figure 16. PCI MASTER READ HIT DRAM
Preliminary Revision 0.1 January 9, 1997
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Figure 17. PCI MASTER READ L1 SNOOP TO DRAM
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Electrical Specifications
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& & /. :5 $'6 ($'6 %5'< &$ %( + ,7 0 $+ 2 /' %2)) $'9
VT82C580VPX
.com
$'6& &2( 7$*: ( 7$ &' 3& /. )5$0 ( ' (96(/ $' &%( ,5 ' < 75'<
Figure 18. PCI MASTER READ HIT L2
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Electrical Specifications
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& & /. :5 $'6 ($'6 %5'< &$ %( + ,7 0 $ + 2 /' %2 )) $'9 $'69
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.com
*:( %:( & ( 7$* : ( 7$ &' 0' 3 & /. )5$0 ( ' ( 9 6 ( / $' &%( ,5 ' < 75'<
Figure 19. PCI MASTER READ L1 SNOOP TO L2
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&&/. :5 $'6 ($'6 %5'< &$ %( + ,7 0 $+2 /' %2))
VT82C580VPX
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&' 0' 5$6 &$6 0:( 3&/. )5$0 ( '(96(/ $' &%( ,5 ' < 75'<
Figure 20. PCI MASTER WRITE DRAM
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Electrical Specifications
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& & /. :5 $'6 ($'6 %5'< &$ %( + ,7 0 $+ 2 /' %2)) &' 0' 5$6 &$6 0:( 3& /.
VT82C580VPX
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)5$0 ( ' (96(/ $' &%(
,5 ' < 75'<
Figure 21. PCI MASTER WRITE HIT L1 SNOOP TO DRAM
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Electrical Specifications
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VT82C580VPX
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7$ &' 0' 5$6 &$6 0:( 3&/. )5$0 ( '(96(/ $' &%( ,5 ' < 75'<
Figure 22. PCI MASTER WRITE HIT L2
Preliminary Revision 0.1 January 9, 1997
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&&/. :5 $'6 ($'6 %5'< &$ %( + ,7 0 $+2 /' %2)) 7$*: (
VT82C580VPX
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7$ &' 0' 5$6 &$6 0:( 3&/. )5$0 ( '(96(/ $' &%( ,5 ' < 75'<
Figure 23. PCI MASTER WRITE HIT L2, L1 HITM
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&&/. :5 $'6 ($'6 %5'< &$ %( + ,7 0 $+2 /' %2)) $'9 7$*: ( 7$ &' 0' 5$6 &$6 0:( 3&/. )5$0 ( '(96(/ $' &%( ,5 ' < 75'<
VT82C580VPX
Figure 24. PCI MASTER WRITE HIT L2 & DIRTY
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VT82C580VPX
PACKAGE MECHANICAL SPECIFICATIONS
PQFP-208

7<3
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7<3

0$;

a
4
Figure 25. Mechanical Specifications - 208-Pin Plastic Flat Package
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Preliminary Revision 0.1 January 9, 1997 -49Package Mechanical Specifications
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PQFP-100
VT82C580VPX

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0$;
73<
a
4
Figure 26. Mechanical Specifications - 100-Pin Plastic Flat Package
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Preliminary Revision 0.1 January 9, 1997 -50Package Mechanical Specifications
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